1. Technical Field of the Invention
The present invention relates to a programmable system device (PSD) which includes both a FLASH module and programmable logic device (PLD) module.
2. Description of Related Art
Reference is now made to FIG. 1 wherein there is shown a block diagram of a prior art programmable system device (PSD) 10. The PSD 10 is an integrated circuit in which is embedded both a FLASH memory module 12 and a programmable logic device (PLD) module 14. The PSD 10 may further include other modules 16.
In a preferred, but not necessarily required, implementation, the PLD cells within the PLD module 14 are built using a series of FLASH cells and a CMOS transistor. Such a design is taught by co-pending and commonly assigned published Application for Patent 20030222309 entitled “Programmable Logic Device Circuit and Method of Making Same”, by A. Roy and L. Fasoli, the disclosure of which is hereby incorporated by reference.
As is well known to those skilled in the art, a FLASH cell within the FLASH memory module 12 requires a multitude positive and negative voltages to be applied, in precise ways, in order to program, erase or read the cell. To that end, the FLASH memory module 12 includes a power supply voltage generator 18 receives analog voltages and clocks that are common for the PSD 10 and utilizes charge pumps and current and voltage regulator circuits well known in the art to generate a multitude of voltages 26 useful in programming, erasing and reading operations. For example, FLASH cells require a voltage, referred to here as VXP, which is the voltage that is applied to a word line of the cell when programming the cell (typically, for a given technology, about 8.75 volts). FLASH cells further require a voltage, referred to here as VXR, which is the voltage that is applied to the word line of the cell when reading the cell (typically, for a given technology, about 4.5 volts). Still further, FLASH cells require a voltage, referred to here as VY, which is the Y-decoding transistor(s) gate voltage (typically, for a given technology, about 4.5 or 9 volts depending on operating mode). FLASH cells also require a voltage, referred to here as VNEG, which is a negative voltage applied to a p-well within which the word line decoder/driver circuit is implemented and to the gate of the cell being erased (typically, for a given technology, about −9 volts). Additionally, FLASH cells require a voltage, referred to here as VPWNEG, which is a negative voltage applied to a p-well within which the FLASH cell is implemented (typically, for a given technology, about −1.2 volts). Also, FLASH cells require a voltage, referred to here as VPD, which is a drain programming voltage applied to the bit lines of the FLASH cell (typically, for a given technology, about 4.25 volts). The foregoing identified voltages are exemplary and it is noted that other voltages may additionally be needed. However, each needed voltage is provided by the power supply voltage generator 18 or is derived from the voltages provided by the power supply voltage generator.
The FLASH memory module 12 further includes a power management logic circuit 20 which contains a section to decode the module operation commands 22 and a microcontroller that, based on the command being decoded, executes a program/erase routine and generates logic signals 24 that are applied to the power supply voltage generator 18. The logic signals 24 relate to a certain operational mode of the FLASH memory module 12 and tell the power supply voltage generator 18 to generate the proper voltages (VXP, VXR, etc., as discussed above) 26 for application to FLASH cells within a FLASH array 28. The module operation commands 22 are generated by a FLASH user interface 30 which receives user commands relating to FLASH memory module 12 operation, understands those commands and the generates the module operation commands 22 which cause implementation of the user commands by the module 12.
Some of the voltages 26 are selectively applied to the FLASH array 28 depending upon the mode of operation being implemented with respect to the FLASH cells. An example of this relates to the VXP and VXR voltages. In a programming mode of operation, the VXP voltage is connected to the word line. In a read mode of operation, on the other hand, the word line receives the VXR voltage. Other examples of selective application of voltages 26 will be recognized by those skilled in the art. To accomplish this selective application of the voltages 26 to the FLASH array 28, the FLASH memory module 12 further includes a first level of switching implemented through a first switching circuit 32 which includes a plurality of individual switches that receive certain ones of the plural voltages 26 and then selectively output certain ones of those voltages 34 for application to the array 28. With respect to the word line example above, an individual switch in the circuit 32 would function to choose between the VXP and VXR voltages depending on whether the array was user selected to be in programming or read mode, respectively. Other voltage switching operations with respect to the voltages 26 will be recognized by those skilled in the art.
The FLASH array 28 may be divided into a plurality of memory banks 36. In an exemplary implementation, two such memory banks 36 (Bank A and Bank B) are shown. Separate control may be exercised over each of the included banks 32, and thus separate control over the application of power supply voltage generator 18 voltages 26 to each bank must be supported. The first switching circuit 32 of the FLASH memory module 12 accordingly may include a separate a set of switches (for example, Set A and Set B) for each included memory bank. Responsive to control signals 38, the switches within the first switching circuit 32 operate make the appropriate voltage 26 selections for application 34 to the array 28 (and more particularly to the banks 36 therein) to implement a desired mode of operation.
Each bank 36 within the array may further include a plurality of sectors 40 within which the FLASH cells are arrayed. To ensure the application of proper voltages at the FLASH cell and driver level, the FLASH array 28 includes a second switching circuit 42. This second switching circuit 42 may include switches that are operable on an individual sector 40 basis, as well as switches that are operable across multiple sectors (for example, a sector group). The second switching circuit 42 operates in a manner similar to the first switching circuit 32 in that it functions responsive to control signals 44 to make the appropriate voltage 26/34 selections for application to the array 28 (and more particularly within the sectors 40 therein) to implement a desired mode of operation.
The control signals 38 and 44 are generated within the FLASH memory module 12 in response to user commands relating to FLASH memory module 12 operation received by the FLASH user interface 30. These control signals 38 and 44 may be generated by the power management logic 20 or by other control logic 46 resident within the FLASH memory module 12.
The PLD module 14 within the PSD 10 includes an array 128 of PLD cells. As discussed above, the PLD cells within the PLD module 14 may be built using a series of FLASH cells and a CMOS transistor. Given such a configuration, the PLD module 14, like the FLASH module 12, would require a multitude positive and negative voltages to be applied, in precise ways, in order to program, erase or read each cell. Even in other known non-FLASH-related configurations, the PLD module 14 would still require access to a number of voltages to ensure proper operation. Thus, the PLD module 14, like the FLASH module 12, uses a power supply voltage generator 118 which receives analog voltages and clocks that are common for the PSD 10 and utilizes charge pumps and voltage regulator schemes well known in the art to generate a multitude of voltages 126 useful in programming, erasing and reading operations. For example, with a PLD module 14 implemented using FLASH technology, the same types of voltages described above and known to those skilled in the art, such as, for example, the VXP voltage (typically, for a given technology, 8.75 volts), the VXR voltage (typically, for a given technology, 4.5 volts), the VY voltage (typically, for a given technology, 4.5 or 9 volts, depending on operational mode), the VNEG voltage (typically, for a given technology, −9 volts), the VPWNEG voltage (typically, for a given technology, 0.8 volts), and the VPD voltage (typically, for a given technology, 4.2 volts), are also needed for the PLD module 14. In the common PSD 10 architecture, the generators 18 and 118 are separately implemented on the integrated circuit because the PLD and FLASH cells are built in a different way (for example, FLASH versus EEPROM or SRAM). The generators 18 and 118 are also separately implemented due to the fact that the voltage requirements of FLASH and PLD are in some operating modes different.
With a separate generator 118, the PLD module 14 further includes its own power management logic circuit 120 which receives module operation commands 122 and translates those commands to values 124 that are applied to the power supply voltage generator 118. The values 124 relate to a certain operational mode of the PLD module 14 and tell the power supply voltage generator 118 to generate the proper voltages (for example, VXP, VXR, etc., as discussed above) 126 for application to PLD cells within the array 128. The module operation commands 122 are generated by a PLD user interface 130 which receives user commands relating to PLD module 14 operation, understands those commands (perhaps through a decoding operation) and the generates the module operation commands 122 which cause implementation of the user commands by the module 14.
Some of the voltages 126 are selectively applied to the PLD array 128 depending upon the mode of operation being implemented with respect to the PLD cells. To accomplish this selective application of the voltages 126 to the PLD array 128, the PLD module 14 further includes a first level of switching implemented through a first switching circuit 132 which includes a plurality of individual switches that receive certain ones of the plural voltages 126 and then selectively output certain ones of those voltages 134 for application to the array 128. Responsive to control signals 138, the switches within the first switching circuit 132 operate make the appropriate voltage 126/134 selections for application to the array 128 to implement a desired mode of operation.
The PLD array 128 may include a plurality of sectors 140 within which the PLD cells are arrayed. To ensure the application of proper voltages at the PLD cell level, the PLD array 128 includes a second switching circuit 142. This second switching circuit 142 may include switches that are operable on an individual sector 140 basis, as well as switches that are operable across multiple sectors (for example, a sector group). The second switching circuit 142 operates in a manner similar to the first switching circuit 132 in that it functions responsive to control signals 144 to make the appropriate voltage 126/134 selections for application to the array 128 (and more particularly within the sectors 140 therein) to implement a desired mode of operation.
The control signals 138 and 144 are generated within the PLD module 14 in response to user commands relating to PLD module 14 operation received by the PLD user interface 130. These control signals 138 and 144 may be generated by the power management logic 120 or by other control logic 146 resident within the PLD module 14.
The PSD 10 architecture illustrated in FIG. 1 leaves much to be desired. The presence of two separate power supply voltage generators 18 and 118 occupies a significant amount of real estate on the integrated circuit chip (for example, due to the duplication of the pump circuitry necessary to generate a plurality of different voltages). Additionally, testing of such an integrated circuit is time consuming. Still further, the presence of large amounts of analog circuitry as is needed in the generators increases the complexity of the chip design, increases the cost of design and manufacture, and increases the risk of defect. Lastly, an integrated circuit containing plural voltage generator circuit consumes a significant amount of power.
A need accordingly exists in the art for an improved power supply solution for use in multi-module integrated circuits like PSDs. There would be an advantage if a single power supply could be provided and shared by the included modules.